In complex integrated circuit devices requiring extensive use of first and second level metal conductors for interconnecting various portions of the integrated circuit, it is occasionally necessary to interconnect portions on opposite sides of an intervening metal conductor. Such interconnections are typically effected by means of a layer of doped silicon which is formed as a tunnel under the intervening metal conductor and insulated therefrom. The desired interconnection is then made to the doped silicon layer on each side of the intervening metal conductor. Such a prior art structure is shown in FIG. 1 which shows a semiconductor device 8, an intervening metal conductor 12, and a layer 14 of doped polycrystalline silicon which is insulated from the conductor 12 by a layer 15. The desired interconnection is achieved by effecting ohmic contact between a metal conductor 16 and the layer 14 on one side of the conductor 12 and similarly, effecting ohmic contact between another metal conductor 18 on the other side of the conductor 12. The required ohmic contact is effected at a plurality of discrete contact points 20 in accordance with standard design rules which are commonly used throughout the industry. Typically, the contact points 20 are square or rectangular and are substantially equally spaced so that the spaces between the contacts are about equal to the length of a contact point, however, substantial variations in these relative lengths often occur. Such arrangements provide sufficient contact area so that the full current carrying capability of the layer 14 is utilized. However, it will be appreciated by those skilled in the art that the doped layer 14 of polycrystalline silicon, at best, has a sheet resistance of about 15 ohms per square resulting in an interconnection that will be unsuitable for certain applications where a low resistance conductor is needed. Heretofore, for such applications and where metal silicides are unacceptable, there has been no way of effecting a low resistance interconnection without increasing the width of the tunnel thereby requiring additional chip space.